VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Paper
•
2505.20302
•
Published
Model Card
Reasoning model specialized for Verilog code.
Model Description
Model card for VeriThoughts-4B
- Developed by: VeriThoughts Team
- Finetuned from model: Qwen/Qwen-4B (LoRA adaptation)
Model Sources
- Repository: https://github.com/wilyub/VeriThoughts
- Paper https://arxiv.org/abs/2505.20302
- Demo: Coming soon!
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